1. Field
Example embodiments relate to a dividing circuit, and more particularly, to a dividing circuit, which can improve its own stability against noise in a phase locked loop (PLL), and a PLL using the dividing circuit.
2. Description of Related Art
In general, it is necessary to control discrete apparatuses or electronic circuits on a computer system or a chip in response to a single reference signal. Therefore, a synchronization circuit for generating an internal clock signal in synchronization with an external reference signal may be designed and embedded on the computer system or chip. A typical example of the synchronization circuit may be a phase locked loop (PLL).
The PLL may detect a phase difference between an input signal and an output signal, outputted from a voltage controlled oscillator (VCO), and determine the frequency and phase of the output signal. In particular, a conventional PLL periodically generates a division input signal based on a same specific edge of an input signal, and compares the output signal with the division input signal to generate an output signal based on the division input signal. The PLL may be widely used to synchronize the frequency of the input signal with that of the output signal